| 摘要 |
On the basis
of single-ended signals based on logic levels, andof differential, in particular common-mode-based, signals,
a circuit arrangement and a corresponding method are proposed, in which it is possible to further reduce the size of tools, which are associated with said type of circuit arrangement and said type of method. |
| 主权项 |
1. A circuit arrangement
with at least one transmission arrangement, to which can be applied:
data signals transportable on at least one data line, wherein on each of the data lines both
single-ended logic-level-based data signals, anddifferential data signals are present, andclock signals transportable on at least one clock line, wherein on each of the clock lines both
single-ended logic-level-based clock signals, anddifferential clock signals are present, and with at least one receiving arrangement, which outputs:
the data signals transportable on the at least one data line, wherein on each of the data lines both
the single-ended logic-level-based data signals, andthe differential data signals are present, andthe clock signals transportable on the at least one clock line, wherein on each of the clock lines both
the single-ended logic-level-based clock signals, andthe differential clock signals are present, wherein the transmission arrangement serializes the single-ended, logic-level-based data and clock signals and the differential data and clock signals to form a common signal stream, and wherein the receiving arrangement deserializes this common signal stream into the single-ended, logic-level-based data and clock signals and the differential data and clock signals. |
