Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby

摘要

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

主权项

1. A method for fabricating an integrated circuit comprising the steps of:
providing a semiconductor substrate having formed thereon first, second, and third sacrificial silicon regions, each of the first, second, and third sacrificial silicon regions having sidewall spacer structures formed along sides thereof, wherein the third sacrificial silicon region has a width that is greater than either a width of the first sacrificial silicon region or a width of the second sacrificial silicon region; removing the first, second, and third sacrificial silicon regions to form first, second, and third trenches between the sidewall spacer structures of each of the first, second, and third sacrificial silicon regions, respectively; depositing an etch-stop layer and a first workfunction material layer within the first, second, and third trenches and over the semiconductor substrate; removing the first workfunction material layer from within the first trench to expose the etch-stop layer in the first trench and leaving the first workfunction material layer in the second and third trenches; depositing a second workfunction material layer within the first trench and over the etch-stop layer in the first trench, and within the second and third trenches and over the first workfunction material layer in the second and third trenches; removing the first and second workfunction material layers from within the third trench to expose the etch-stop layer in the third trench, leaving the first and second workfunction material layers in the second trench, and leaving the second workfunction material layer in the first trench; depositing a metal fill material within the first and second trenches and over the second workfunction material layer in the first and second trenches, and within the third trench over the etch-stop layer in the third trench, wherein the metal fill material is deposited to a thickness such that the first and second trenches are completely filled with the metal fill material, but the third trench is not completely filled with the metal fill material; and depositing a silicon material layer within the third trench.