Register file write ring oscillator

摘要

Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.

主权项

1. A system, comprising:
a processing device; one or more register files, wherein each one of the one or more register files comprises a plurality of register cells; and a test circuit configured to operate the read and write paths of at least one of the one or more register files responsively to a test mode signal; wherein the test circuit includes a frequency divider coupled to an output of the selected one of the plurality of data storage cells, wherein the frequency divider is configured to reduce a frequency of data read from a selected one of the plurality of register cells; wherein to operate the read and write paths of the at least one of the one or more register files, the test circuit is further configured to: invert data read from a given register cell included in the at least one of the one or more register files to generate new data; and store the new data in the given register cell.