发明名称 Semiconductor device and driving method thereof
摘要 An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.
申请公布号 US9230683(B2) 申请公布日期 2016.01.05
申请号 US201313864476 申请日期 2013.04.17
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Takemura Yasuhiko
分类号 G11C29/12;G11C29/04;G11C29/52;G11C11/405;G06F11/10;G11C16/04 主分类号 G11C29/12
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a configuration memory, and a cyclic redundancy check memory comprising a plurality of memory elements being in a matrix, each memory element including: a plurality of transistors;a capacitor; anda data storage portion configured to store data for an error detection, wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, wherein the cyclic redundancy check memory has a lower error rate than the configuration memory, and wherein the semiconductor device is configured to conduct: calculating a remainder;storing the remainder in the cyclic redundancy check memory;detecting an error of an i-th row with use of the remainder by a cyclic redundancy check;performing processing of an i+l-th row if there is no error in the i-th row;writing data to be input to the i-th row which is stored in the configuration memory if there is an error in the i-th row; andrepeating the step of detecting an error and the step of writing data until no error is detected.
地址 Atsugi-shi, Kanagawa-ken JP