发明名称 Nonvolatile semiconductor memory device and control method thereof
摘要 This nonvolatile semiconductor memory device comprises a memory cell array including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, and further comprises a control unit for controlling a voltage applied to the bit lines and word lines. The memory cell includes a variable resistance element and a rectifier element. The control unit provides a first potential difference to a selected memory cell via a selected bit line and a selected word line, and then provides a second potential difference to the selected memory cell via the selected bit line and the selected word line, the second potential difference being for erasing a residual charge.
申请公布号 US9230646(B2) 申请公布日期 2016.01.05
申请号 US201314020583 申请日期 2013.09.06
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Sonehara Takeshi
分类号 G11C13/00 主分类号 G11C13/00
代理机构 Holtz, Holtz, Goodman & Chick PC 代理人 Holtz, Holtz, Goodman & Chick PC
主权项 1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plurality of bit lines and the plurality of word lines; and a control unit configured to control a voltage applied to the bit lines and word lines, the memory cell including a variable resistance element and a rectifier element, and the control unit being configured to: apply a third voltage to a selected bit line and apply a fourth voltage to a selected word line; apply a fifth voltage different from the third voltage to unselected bit lines excluding the selected bit line and apply a sixth voltage different from the fourth voltage to unselected word lines excluding the selected word line; and provide a selected memory cell with a first potential difference as a difference between the third voltage and the fourth voltage at a first operation, and provide the memory cell where the first operation has finished with a second potential difference as a difference between the third voltage and the sixth voltage or a difference between the fourth voltage and the fifth voltage, the second potential difference being for erasing a residual charge.
地址 Tokyo JP