GENERATING COMBINED BUS CLOCK SIGNALS USING ASYNCHRONOUS MASTER DEVICE REFERENCE CLOCKS IN SHARED BUS SYSTEMS, AND RELATED METHODS, DEVICES, AND COMPUTER-READABLE MEDIA

摘要

Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

主权项

1. A method for generating combined bus clock signals, comprising:
detecting a start event by each master device of one or more master devices communicatively coupled to a shared clock line of a shared bus; sampling, by each master device, a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device; determining, by each master device, whether the plurality of shared clock line values is identical; and responsive to determining that the plurality of shared clock line values is identical, driving, by each master device, a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.