MEMORY PHYSICAL LAYER INTERFACE LOGIC FOR GENERATING DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMMANDS WITH PROGRAMMABLE DELAYS

摘要

A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words.

主权项

1. An apparatus comprising:
a memory physical layer interface (PHY) to couple to an external memory; a plurality of registers implemented in association with the memory PHY, the plurality of registers to store at least one instruction word that indicates at least one command and at least one delay; and a first training engine implemented in the memory PHY to generate, based on said at least one instruction word, at-speed programmable sequences of commands for delivery to the external memory and to delay the commands based on said at least one delay.