| 摘要 |
A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor. |
| 主权项 |
1. A method, implemented on a computer, for allowing non-cacheable loads in a hardware transactional memory environment, wherein the computer comprises a processor in communication with a memory, wherein transactional loads or stores by the processor are monitored for transactional execution (TX) conflicts in a cache of the hierarchical cache subsystem, the method comprising:
accepting a request, by the processor, to execute a TX transaction; based on execution, by the processor, of a non-cacheable load instruction for loading second memory data of the transaction, loading an address of the second memory data into a non-cache-monitor for monitoring memory conflicts of non-cached lines, the non-cache monitor for monitoring memory conflicts of non-cached lines; and aborting the TX transaction based on the non-cache monitor detecting a memory conflict from another processor, the memory conflict comprising requesting an access, by the other processor, to the address monitored by the non-cache monitor. |
