| 发明名称 |
CO-PROCESSOR MEMORY ACCESSES IN A TRANSACTIONAL MEMORY |
| 摘要 |
Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction. |
| 申请公布号 |
US2015378905(A1) |
申请公布日期 |
2015.12.31 |
| 申请号 |
US201514825264 |
申请日期 |
2015.08.13 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Bradbury Jonathan D.;Gschwind Michael Karl;Schwarz Eric M.;Shum Chung-Lung K.;Slegel Timothy J. |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A method for monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor, the method comprising:
executing, by the processor, a transactional memory (TM) transaction, the executing comprising: receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation; saving, by the processor, the memory address range; and based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, aborting the TM transaction. |
| 地址 |
Armonk NY US |
