发明名称 MEMORY DEVICE HAVING ERROR CORRECTION LOGIC
摘要 Data is read from memory cells in the memory device. The read data is transferred over a link to a memory controller that is external of the memory device. While the transferring of the read data is ongoing, error detection of the read data is performed inside the memory device using an error correction code.
申请公布号 US2015378823(A1) 申请公布日期 2015.12.31
申请号 US201314767479 申请日期 2013.03.25
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 Lesartre Gregg B.
分类号 G06F11/10;G06F3/06 主分类号 G06F11/10
代理机构 代理人
主权项 1. A memory device comprising: a communication interface to communicate over a link to a memory controller that is external of the memory device; data access logic to read data from memory cells, wherein the communication interface is to output the read data through the communication interface over the link; and error correction logic to perform error detection of the read data using an error correction code associated with the read data, wherein the error correction logic is to perform the error detection concurrently with portions of the read data being communicated over the link.
地址 Houston TX US