发明名称 |
FREQUENCY SYNTHESIZER FOR ACHIEVING FAST RE-LOCK BETWEEN ALTERNATE FREQUENCIES IN LOW BANDWIDTH PLLS |
摘要 |
A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot. |
申请公布号 |
US2015381190(A1) |
申请公布日期 |
2015.12.31 |
申请号 |
US201514753940 |
申请日期 |
2015.06.29 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
GOYAL Jagdish Chand;THIAGARAJAN Krishnaswamy;JANARDHANAN Jayawardan;MANIAN Srikanth |
分类号 |
H03L7/093;H03L7/089;H03L7/081;H04B1/40 |
主分类号 |
H03L7/093 |
代理机构 |
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代理人 |
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主权项 |
1. A frequency synthesizer, comprising:
a reference frequency scaler configured to generate a first reference frequency and a second reference frequency; and a phase locked loop (PLL) coupled to the reference frequency scaler, the PLL configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot; wherein the PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot. |
地址 |
Dallas TX US |