发明名称 SIMULTANEOUS TRANSITION TESTING OF DIFFERENT CLOCK DOMAINS IN A DIGITAL INTEGRATED CIRCUIT
摘要 Implementations of the present disclosure involve an apparatus and/or method for conducting simultaneous transition testing of different clock domains of a microprocessor design at different frequencies through a controlled order of clock pulses in each domain. In general, a microelectronic design utilizes test control circuitry associated with each clock domain of the design to conduct simultaneous transition testing of the clock domains. The testing control circuitry associated with each clock domain of the microelectronic design further allows for the testing device to delay testing within a particular clock domain. By delaying the testing within a particular clock domain, the testing of the various clock domains can be synchronized. Through these testing procedures, the amount of time required to perform the ATPG testing of a microelectronic design may be greatly reduced.
申请公布号 US2015377960(A1) 申请公布日期 2015.12.31
申请号 US201414316468 申请日期 2014.06.26
申请人 Oracle International Corporation 发明人 Vahidsafa Ali;Mistely Roger Charles
分类号 G01R31/3177 主分类号 G01R31/3177
代理机构 代理人
主权项 1. A method of automatic test pattern generation (ATPG) testing of a microelectronic circuit, the method comprising: generating a test program comprising a plurality of instructions to conduct ATPG testing of a plurality of clock domains of the microelectronic circuit, wherein a first clock domain of the plurality of clock domains operates on a first clock signal with a first frequency and a second clock domain of the plurality of clock domains operates on a second clock signal with a second frequency, the first frequency different from the second frequency; and transmitting a first clock domain testing instruction of the plurality of instructions to a first test control circuit associated with first clock domain and a second clock domain testing instruction of the plurality of instructions to a second test control circuit associated with second clock domain, wherein the first clock domain testing instruction and the second clock domain testing instruction cause the first clock domain and the second clock domain to undergo ATPG testing simultaneously.
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