发明名称 |
IMAGE PROCESSOR |
摘要 |
An image processor includes: a first division control information acquiring circuit configured to acquire division control information of a first chip; a second division control information acquiring circuit configured to acquire division control information of a second chip; a division process control circuit configured to determine a ratio at which a process is performed by the first image processing circuit and a ratio at which a process is performed by the second image processing circuit, based on the division control information of the first chip and the division control information of the second chip; a division circuit configured to divide data to be subjected to image processing into first-chip data and second-chip data at the determined ratios; the first image processing circuit configured to perform image processing on the first-chip data; and the second image processing circuit configured to perform image processing on the second-chip data. |
申请公布号 |
US2015379675(A1) |
申请公布日期 |
2015.12.31 |
申请号 |
US201514747738 |
申请日期 |
2015.06.23 |
申请人 |
Olympus Corporation |
发明人 |
Yonemoto Tomonori;Ikeda Hideru;Funakoshi Naoto |
分类号 |
G06T1/20;H04N5/232 |
主分类号 |
G06T1/20 |
代理机构 |
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代理人 |
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主权项 |
1. An image processor comprising:
a first division control information acquiring circuit configured to acquire division control information of a first chip having a first image processing circuit; a second division control information acquiring circuit configured to acquire division control information of a second chip having a second image processing circuit; a division process control circuit configured to determine a ratio at which a process is performed by the first image processing circuit and a ratio at which a process is performed by the second image processing circuit, based on the division control information of the first chip and the division control information of the second chip; a division circuit configured to divide data to be subjected to image processing into first-chip data and second-chip data at the ratios determined by the division process control circuit; the first image processing circuit configured to perform image processing on the first-chip data; and the second image processing circuit configured to perform image processing on the second-chip data. |
地址 |
Tokyo JP |