TFT ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

摘要

A TFT array substrate is disclosed. The array substrate includes gate lines, first and second gate driving circuits, first, second, third, and fourth clock signal lines, first and second initial signal lines, first and second initial transistors, and first, second, third, and fourth clock transistors. The first gate driving circuit includes m stages of first repeating units. The second gate driving circuit includes n stages of second repeating units. Where m and n are positive integers, and 2≦m, 2≦n.

主权项

1. A TFT array substrate, comprising:
a plurality of gate lines; a first gate driving circuit; a second gate driving circuit; a first clock signal line; a second clock signal line; a third clock signal line; a fourth clock signal line; a first initial signal line; a second initial signal line, a first initial transistor; a second initial transistor; a first clock transistor; a second clock transistor; a third clock transistor; and a fourth clock transistor, wherein:
the first gate driving circuit comprises m stages of first repeating units, wherein each stage of first repeating unit comprises:
a first shift register, wherein the first shift register comprises a first input terminal, a first clock signal terminal, a third clock signal terminal, and a first output terminal connected to the corresponding gate line;the second gate driving circuit comprises n stages of second repeating units, wherein each stage of second repeating unit comprises:
a second shift register, wherein the second shift register comprises a second input terminal, a second clock signal terminal, a fourth clock signal terminal, and a second output terminal connected to the corresponding gate line;a drain electrode of the first initial transistor is electrically connected to a first initial signal line, a source electrode of the first initial transistor is electrically connected to the first input terminal of the first shift register from the first stage of first repeating unit, and a gate electrode of the first initial transistor is electrically connected to a first control line;a drain electrode of the second initial transistor is electrically connected to the source electrode of the first initial transistor, the second input terminal of the second shift register from the first stage of second repeating unit is electrically connected to the second initial signal line via a source electrode of the second initial transistor, and a gate electrode of the second initial transistor is electrically connected to a second control line;in the each stage of first repeating unit:
a drain electrode of the first clock transistor is electrically connected to the first clock signal line, a gate electrode of the first clock transistor is electrically connected to the first control line, and a source electrode of the first clock transistor is electrically connected to the first clock signal terminal;a drain electrode of the third clock transistor is electrically connected to the third clock signal line, a gate electrode of the third clock transistor is electrically connected to the first control line, and a source electrode of the third clock transistor is electrically connected to the third clock signal terminal;in the each stage of second repeating unit:
a drain electrode of the second clock transistor is electrically connected to the source electrode of the first clock transistor, a gate electrode of the second clock transistor is electrically connected to the second control line, and the second clock signal terminal is electrically connected to the second clock signal line via a source electrode of the second clock transistor;a drain electrode of the fourth clock transistor is electrically connected to the source electrode of the third clock transistor, a gate electrode of the fourth clock transistor is electrically connected to the second control line, and the fourth clock signal terminal is electrically connected to the fourth clock signal line via a source electrode of the fourth clock transistor; andm and n are positive integers, and 2≦m, 2≦n.