MEMORY CONTROLLER

摘要

A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

主权项

1. A memory controller for reading data from a memory, wherein the memory has an access latency of ‘L’ memory clock cycles, the controller comprising:
a FIFO (first in first out) buffer for receiving data read from the memory; a clock module for providing a memory clock signal to the memory and to the FIFO buffer; a control signal generation module for asserting a control signal and applying said control signal to the memory; a counter for determining an assertion time of said control signal as a function of a number ‘N’ of cycles of the memory clock signal; and a data sampling module coupled to the counter and to the FIFO buffer for sampling an output of the FIFO buffer at a point in time that is a function of N and L.