发明名称 DETECTING CACHE CONFLICTS BY UTILIZING LOGICAL ADDRESS COMPARISONS IN A TRANSACTIONAL MEMORY
摘要 A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.
申请公布号 US2015378895(A1) 申请公布日期 2015.12.31
申请号 US201414317394 申请日期 2014.06.27
申请人 International Business Machines Corporation 发明人 Gschwind Michael Karl;Schwarz Eric M.;Shum Chung-Lung K.;Slegel Timothy J.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项 1. A computer system for determining whether to abort or continue a transaction based on logical addresses, comprising: a memory; and a first processor in communication with the memory, the first processor having a dynamic address translation mechanism for translating logical addresses into real memory addresses, wherein the computer system is configured to perform a method comprising: determining, by the first processor, that a first logical address range has a common relationship with real memory addresses for all programs running on the computer system;executing, by a first thread of the first processor, a first transaction for accessing memory locations within the first logical address range;detecting, by the first processor, whether a store operation conflicts with the first transaction by comparing a logical address of the store operation with the first logical address range;based on the logical address of the store operation being within the first logical address range, aborting, by the first processor, the first transaction, and continuing execution of the store operation; andbased on the logical address of the store operation not being within the first logical address range, continuing, by the first processor, execution of the first transaction, and continuing execution of the store operation.
地址 Armonk NY US