发明名称 |
DIGITAL AGC CONTROL METHOD AND FEEDBACK CONTROL APPARATUS |
摘要 |
A digital AGC control method and feedback control apparatus that enable appropriate feedback control in response to reference input values of various magnitudes are provided. The method comprises a first step in which a digital AGC unit 11 outputs a setting value in accordance with a reference input value, a second step in which a PI control unit 12 calculates an operation amount of a controlled object 16 using the setting value, a third step in which a DAC 13 generates an output signal Y representing the operation amount, a fourth step in which a gain regulator 14 and an ADC 15 calculate a measurement value M of the controlled object; and a fifth step in which the measured value M is input to the digital AGC unit 11. |
申请公布号 |
US2015381127(A1) |
申请公布日期 |
2015.12.31 |
申请号 |
US201314767449 |
申请日期 |
2013.12.26 |
申请人 |
TOYO SYSTEM CO., LTD. |
发明人 |
MUNAKATA Ichirou;SHOJI Hideki |
分类号 |
H03G3/00 |
主分类号 |
H03G3/00 |
代理机构 |
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代理人 |
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主权项 |
1. A digital AGC control method comprising:
a first step in which an AGC unit outputs a setting value in accordance with a reference input value; a second step in which a control unit calculates an operation amount of a controlled object using the setting value; a third step in which an output unit generates an output signal representing the operation amount and outputs it to the controlled object; a fourth step in which a measuring unit calculates an operation measurement value of the controlled object; and a fifth step in which the measured value is input to the AGC unit, said first step including: a sixth step in which the AGC unit stores the reference input value in a first register, stores the measured value input in the fifth step in a second register, and calculates and stores in a third register a deviation between the reference input value stored in the first register and the measured value; a seventh step in which a number of consecutive bits, other than a sign bit, of “0” value among higher-order bits in the first register is detected; and an eighth step in which the deviation stored in the third register is shifted left by a number of bits in accordance with the number of bits detected in the seventh step to generate a deviation setting value as the setting value. |
地址 |
Iwaki-shi, Fukushima JP |