RESISTIVE MEMORY WRITE OPERATION WITH MERGED RESET

摘要

In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

主权项

1. A method for writing a memory device, comprising:
dequeuing a number greater than one of cachelines to perform write operations in a memory device, wherein each cacheline includes a row of memory cells, each memory cell controlled by three separate control lines, wherein writing to a first memory cell state takes longer than writing to a second memory cell state; setting all of the memory cells of the number of cachelines to the first memory cell state in a single write operation; and executing write operations to the number of cachelines individually to selectively write memory cells of the respective cachelines to the second memory cell state.