TRANSACTIONAL EXECUTION PROCESSOR HAVING A CO-PROCESSOR ACCELERATOR, BOTH SHARING A HIGHER LEVEL CACHE

摘要

A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. A processor may have a corresponding accelerator that performs operations on behalf of the processor. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected, and the corresponding cache lines are invalidated. For a successfully completing transaction, the corresponding cache lines are committed and the data from store operations is stored.

主权项

1. A method for detecting conflicts and managing transaction execution (TX) memory, by a hierarchical cache of a multi-processor system, the hierarchical cache comprising a plurality of local caches and a higher level cache. wherein each local cache is associated with a corresponding single processor, wherein each cache comprises a cache controller, wherein the higher level cache is any one of a shared cache associated with a plurality of processors and a non-shared cache associated with a single processor, wherein the single processor is any one of a single thread core and a multi-threaded core, wherein the higher level cache supports any one of processors and processors having corresponding accelerators, the method comprising:
beginning execution of a first transaction, by a first processor thread, the first transaction comprising memory access instructions; causing, by the first transaction, an accelerator co-processor associated with the first processor to perform an accelerator operation; and setting transaction indicators, by the higher level cache, in the higher level cache based on corresponding cache lines being accessed by memory-operand-access operations of first instructions of the first transaction, the first transaction indicators comprising first read-set indicators and first write-set indicators, wherein store data of memory-operand-access operations are stored in the local cache; setting transaction indicators associated with the first transaction in the higher level cache, based on corresponding cache lines being accessed by accelerator co-processor operations, wherein store data of store operations of the accelerator co-processor operations bypasses the local cache; based on determining, by the higher level cache, that a memory conflict has occurred associated with a first cache line of the higher level cache, causing the first transaction to abort and invalidating cache lines of the higher level cache having the first write-set indicators; and based on the first transaction ending, committing cache lines of the higher level cache having the first write-set indicators.