TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION

摘要

Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

主权项

1. A non-transitory machine readable storage medium encoded with computer program code, such that when the computer program code is executed by a computer, the computer program code causes the computer to perform operations comprising:
generating a conflict graph from a layout for a layer of a semiconductor device, said conflict graph including:
a plurality of nodes, each node representing a polygon of said layout, anda plurality of links, each link connecting two of said nodes and corresponding to a distance between adjacent polygons, the distance being less than a minimum inter-pattern separation distance using a single photomask; and converting said conflict graph to a simplified conflict graph, wherein said converting includes assigning two of said nodes to a first photomask and combining said two nodes; wherein the computer is configured to output mask assignment data based on the simplified conflict graph indicating that the layout is decomposable for triple pattern lithography, and the mask assignment data are used to fabricate at least one photomask for patterning the layer of the semiconductor device.