| 发明名称 |
CACHING DATA IN A MEMORY SYSTEM HAVING MEMORY NODES AT DIFFERENT HIERARCHICAL LEVELS |
| 摘要 |
A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes. |
| 申请公布号 |
US2015378913(A1) |
申请公布日期 |
2015.12.31 |
| 申请号 |
US201314764651 |
申请日期 |
2013.03.20 |
| 申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
Jouppi Norman P.;Li Sheng;Chen Ke |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory system comprising:
a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache, wherein a memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels, and wherein the memory nodes are to cooperate to decide which if any of the memory nodes is to cache data of a given one of the memory nodes. |
| 地址 |
Houston TX US |
