发明名称 SYSTEM AND METHODS FOR AUTOMATED DETECTION OF INPUT AND OUTPUT VALIDATION AND RESOURCE MANAGEMENT VULNERABILITY
摘要 <p>In an example embodiment, a system analyzes a set of computer routines. The system may perform an analysis including a determination of a likelihood of vulnerability to unexpected behavior for one or more computer routines of the set. Based upon the analysis, the system may identify one or more computer routines of the set having the likelihood of vulnerability. The system may asynchronously and dynamically manipulate at least one of the one or more computer routines through a testing technique. The system may determine unexpected behavior of at least one of the one or more computer routines.</p>
申请公布号 WO2015200511(A1) 申请公布日期 2015.12.30
申请号 WO2015US37471 申请日期 2015.06.24
申请人 VIRSEC SYSTEMS, INC. 发明人 GUPTA, SATYA VRAT
分类号 G06F21/57;G06F11/36 主分类号 G06F21/57
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