| 摘要 |
A plurality of registers (222) implemented in association with a memory physical layer interface (PHY) (140, 205) can be used to store one or more instruction words (300) that indicate one or more commands and one or more delays (415, 515, 535, 540). A training engine (220) implemented in the memory PHY can generate at-speed programmable sequences of commands (410, 420, 430, 510, 520, 525) for delivery to an external memory (210) and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words. |
