发明名称 WAIT-FREE ALGORITHM FOR INTER-CORE, INTER-PROCESS, OR INTER-TASK COMMUNICATION
摘要 A method and system are presented for providing deterministic inter-core, inter-process, and inter-thread communication between a reader and a writer. The reader and writer communicate by passing data through a shared memory using double buffering of double buffers. The shared memory includes a first double buffer and a second double buffer. Both double buffers include a first low level buffer and a second low level buffer. Using double buffering of the double buffers, both the reader and the writer may simultaneously access the shared memory.
申请公布号 EP2959386(A1) 申请公布日期 2015.12.30
申请号 EP20140709575 申请日期 2014.02.24
申请人 BARCO NV 发明人 MORTIER, PETER
分类号 G06F9/54 主分类号 G06F9/54
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