| 摘要 |
A method for the automated manufacture of an electronic circuit tolerant to faults by temporal redundancy of maximum order N, comprising a step implemented by computer, which involves replacing any memory cell of the circuit with a memory block (40) comprising a chain of memory cells in series, and a selection block which selects, in a temporal redundancy mode of order n1, n1 ∈ [1,N], as output data of the memory block, the majority content of n1 cells of the block, and can further deliver a fault signal if the content of the n1 cells differs. Said method is characterised in that the inserted memory blocks allow dynamic switching from a temporal redundancy mode of order n1 to any other mode of order n2. Said method for N=2, in association with a recording mechanism with backward recovery, makes it possible to mask an error with only double redundancy instead of triple redundancy. |
