Memory access control circuit, prefetch circuit, memory device and information processing system

摘要

Disclosed herein is a memory access control circuit including: a determination section adapted to determine whether a target requested by a first wraparound memory access request from a processor is stored in a prefetch buffer; a request generation section adapted to generate a second wraparound memory access request including the target if it is determined that the target is not stored in the prefetch buffer; and an address conversion section adapted to convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request.

主权项

1. A memory access control circuit comprising:
one or more processors operable to:
determine whether a target, requested by a first wraparound memory access request by the one or more processors to a memory, is stored in a prefetch buffer; generate a second wraparaound memory access request, by the prefetch buffer to the memory, including the target based on determining that the target is not stored in the prefetch buffer;and covert a start address of the first wraparound memory access request for use as a start address of the second wraparound memory access request in an event a wraparound size of the first wraparound memory access request by the one or more processors is different from a wraparound size of the second wraparound memory access request by the prefetch buffer;wherein the wraparound size of the one or more processors is 2m bursts, and m bits starting from the least significant bit of the start address of the first wraparound memory access request are replaced with zeroes to generate the start address of the second wraparound memory access request, wherein a value of m is based on the wraparound size of the first memory access request.