Adjustable buffer circuit

摘要

A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.

主权项

1. A common mode logic (CML) buffer device comprising:
a differential input signal pair that includes a first input and a second input; a differential output signal pair that includes a first output and a second output; a current source; a reference voltage; a first metal-oxide-semiconductor (MOS) transistor pair including:
a first MOS transistor with a gate connected to the first input and connected in series between the current source and the first output, anda second MOS transistor with a gate connected to the second input and connected in series between the current source and the second output; a second MOS transistor pair including:
a third MOS transistor connected in series between the reference voltage and the first output, anda fourth MOS transistor connected in series between the reference voltage and the second output; a first adjustment circuit configured to adjust, in response to a control signal, a first resistance value between the first output and a gate of the third MOS transistor; and a second adjustment circuit configured to adjust, in response to the control signal, a second resistance value between the second output and a gate of the fourth MOS transistor.