Method and apparatus for bit-line sensing gates on an SRAM cell

摘要

A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (SRAM) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.

主权项

1. A circuit comprising:
a six transistor static random access memory (SRAM) cell comprising:
a first inverter cross-coupled to a second inverter,a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, anda second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; anda plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor, wherein the plurality of bit-line sensing transistors comprises:
a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate;a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line;a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; anda sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line.