发明名称 |
Process design to improve transistor variations and performance |
摘要 |
The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another. |
申请公布号 |
US9224814(B2) |
申请公布日期 |
2015.12.29 |
申请号 |
US201414156515 |
申请日期 |
2014.01.16 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Yu Tsung-Hsing;Liu Chia-Wen;Hsu Yeh;Huang Shih-Syuan;Goto Ken-Ichi;Wu Zhiqiang |
分类号 |
H01L29/08;H01L29/78;H01L29/66;H01L21/306;H01L21/265;H01L21/02;H01L29/16 |
主分类号 |
H01L29/08 |
代理机构 |
Eschweiler & Associates, LLC |
代理人 |
Eschweiler & Associates, LLC |
主权项 |
1. A method of forming a transistor device, comprising:
forming a well region within a semiconductor substrate; selectively etching the semiconductor substrate to form a recess within the well region along a top surface of the semiconductor substrate; selectively performing a carbon implantation within the recess to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form one or more epitaxial layers within the recess at positions overlying the carbon implantation region, wherein the one or more epitaxial layers comprise a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer; forming a gate structure onto the silicon epitaxial layer, wherein the gate structure comprises a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer; and forming a source region and a drain region on opposing sides of the gate structure, such that a channel region comprising the one or more epitaxial layers, which is arranged under the gate structure, separates the source region from the drain region. |
地址 |
Hsin-Chu TW |