On-chip controller and a system-on-chip

摘要

An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip.

主权项

1. An on-chip clock controller, comprising:
a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip; and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip, wherein the first domain clock generator comprises: a timing control logic circuit configured to be initialized in response to a scan clock enable signal, and generate a functional clock enable timing control signal in response to the first clock-control bits; a scan clock enable register configured to generate the scan clock enable signal synchronized with the first data scan clock in response to a scan mode signal; a scan clock gate configured to gate the first data scan clock in response to the scan clock enable signal; a functional clock enable register configured to generate a functional clock enable signal synchronized with the first functional clock in response to the scan mode signal and the functional clock enable timing control signal; a first multiplexer configured to selectively output the first data scan clock provided from the scan clock gate or the first functional clock in response to the functional clock enable signal; and a second multiplexer configured to selectively output, as the first internal clock, a clock outputted from the first multiplexer or the first functional clock in response to a test mode signal.