In-processor dynamic address redirection table for substituting instruction strings

摘要

A data processor includes a redirection dynamic address redirection table (DART) for redirecting instruction fetches from an original memory location with an original address to a target memory location with a target address.

主权项

1. A data processor comprising:
a fault detector to determine whether an instruction is subject to a higher priority fault than a dynamic address redirection table (DART)-triggered fault, an address generator including:
a dynamic address redirection table (DART) for converting a virtual instruction address to a virtual trace address when the instruction is not subject to the higher priority fault, in which:
the virtual instruction address identifies an instruction location in memory of the instruction, the instruction location also having a physical instruction address,andthe virtual trace address identifies a trace location in memory of a trace of instructions for emulating the instruction, the trace location also having a physical trace address, anda translation lookaside buffer (TLB) coupled to the DART to convert the virtual trace address to the physical trace address; and an instruction pipeline for receiving and executing the trace.