Programmable logic device and semiconductor device

摘要

To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

主权项

1. A programmable logic device comprising:
a programmable switch element comprising:
an input terminal;an output terminal;a first transistor;a second transistor;an insulating film over the first transistor and the second transistor;a third transistor over the insulating film;a fourth transistor over the insulating film;a fifth transistor;a sixth transistor;a seventh transistor over the insulating film; andan eighth transistor over the insulating film, wherein a first terminal of the first transistor is electrically connected to the input terminal, wherein a second terminal of the first transistor and a first terminal of the second transistor are electrically connected to each other, wherein a second terminal of the second transistor is electrically connected to the output terminal, wherein a first terminal of the third transistor is electrically connected to a gate of the first transistor, wherein a first terminal of the fourth transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the fifth transistor is electrically connected to the input terminal, wherein a second terminal of the fifth transistor and a first terminal of the sixth transistor are electrically connected to each other, wherein a second terminal of the sixth transistor is electrically connected to the output terminal, wherein a first terminal of the seventh transistor is electrically connected to a gate of the fifth transistor, wherein a first terminal of the eighth transistor is electrically connected to a gate of the sixth transistor, wherein a second terminal of the third transistor and a second terminal of the seventh transistor are electrically connected to each other, and wherein a gate of the fourth transistor and a gate of the eighth transistor are electrically connected to each other.