Clock signal networks for structured ASIC devices

摘要

Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

主权项

1. Clock distribution circuitry for an integrated circuit, the clock distribution circuitry comprising:
a deterministic clock distribution portion; a user-configurable clock distribution conductor located within a predetermined area of the integrated circuit; and configurable logic elements (LEs) on the predetermined area of the integrated circuit, the configurable LEs being custom-configurable by a user to selectably be configured to: (a) function as clock distribution buffer circuitry, for routing, through the user-configurable clock distribution conductor, a clock signal from the deterministic clock distribution portion to clock utilization circuitry within the predetermined area of the integrated circuit, and (b) perform logic functions when not functioning as the clock distribution buffer circuitry.