发明名称 Non-volatile memory circuit
摘要 A non-volatile memory circuit includes a non-volatile memory having a first source and drain region having a non-LOCOS offset structure and a second source and drain region having a LOCOS offset structure. A pair of switch circuits are connected in parallel to the respective first and second source and drain regions for switching voltages applied to the first and second source and drain regions so that the first source and drain region serves as a drain and the second source and drain region serves as a source in a writing mode, the second source and drain region serves as a drain and the first source and drain region serves as a source in a reading mode, and equal voltages are applied to the first source and drain region and the second source and drain region in a retention mode.
申请公布号 US9224872(B2) 申请公布日期 2015.12.29
申请号 US201314097296 申请日期 2013.12.05
申请人 SEIKO INSTRUMENTS INC. 发明人 Kawakami Ayako
分类号 H01L29/788;H01L29/423 主分类号 H01L29/788
代理机构 Adams & Wilks 代理人 Adams & Wilks
主权项 1. A non-volatile memory circuit comprising: a non-volatile memory having a one-sided LOCOS offset structure, the non-volatile memory comprising: a first source and drain region having a non-LOCOS offset structure, which is different from a LOCOS offset structure; anda second source and drain region having the LOCOS offset structure; switch circuits respectively connected to the first source and drain region and the second source and drain region; a floating gate across which the first source and drain region and the second source and drain region are disposed; a capacitive coupling oxide film formed on a part of the floating gate; a control gate capacitively coupled with the part of the floating gate through intermediation of the capacitive coupling oxide film; and a lightly doped region disposed between and in contact with a side of the first source and drain region and an end of the floating gate.
地址 JP