Guarding ring structure of a high voltage device and manufacturing method thereof

摘要

The present invention provides a guarding ring structure of a semiconductor high voltage device and the manufacturing method thereof. The guarding ring structure comprises a first N type monocrystalline silicon substrate (3), a second N type monocrystalline silicon substrate (8), a discontinuous oxide layer (2), a metal field plate (1), a device region (9), multiple P+ type diffusion rings (5) and an equipotential ring (4). The second N type monocrystalline silicon substrate (8) is a single N type crystalline layer epitaxially formed on the first N type monocrystalline silicon substrate (3) and has lower doping concentration than the first N type monocrystalline silicon substrate (3). N type diffusion rings (6) are embedded in the inner side of the P+ type diffusion rings (5) and are fully depleted at zero bias voltage. The guarding ring structure can achieve the same withstand voltage with less area and design time.

主权项

1. A guarding ring structure of a semiconductor high voltage device comprising:
a first N type monocrystalline silicon substrate (3); a second N type monocrystalline silicon substrate (8) which is an N type single crystalline layer formed on the first N monocrystalline silicon substrate (3); the doping concentration of the second N monocrystalline silicon substrate (8) is lower than that of the first N monocrystalline silicon substrate (3); a discontinuous oxide layer (2) disposed on the surface of the second N type monocrystalline silicon substrate (8); a metal field plate (1) partially covering the exposed surface of the second N type monocrystalline silicon substrate (8) and the oxide layer (2); a device region (9) embedded in the second N monocrystalline silicon substrate (8); multiple P+ type diffusion rings (5) embedded in the second N type monocrystalline silicon, wherein the P+ type diffusion ring (5) adjacent to the device region (9) is an innermost ring which surrounds and centers the device region (9) and is grounded when the device region (9) works; the other P+ type diffusion rings (5) are concentric with the innermost ring and are floated when the device region (9) works; an equipotential ring (4) embedded in the second N type monocrystalline silicon substrate (8) and surrounding the periphery of the multiple P+ type diffusion rings (5); at least one N type diffusion ring (6) fully depleted at zero bias voltage, each N type diffusion ring (6) is embedded in one of the P+ diffusion rings (5) and surrounds and centers the device region (9).