Semiconductor memory apparatus with main memory blocks and redundant memory blocks sharing a common global data line

摘要

A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled.

主权项

1. A semiconductor memory apparatus comprising:
a memory area comprising a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to transmit and receive data to and from the outside through a common global data line which is any one of the plurality of global data lines; and a controller configured to be electrically connected with the memory area, and configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled; wherein, as the redundancy program mode, the redundancy read mode, or the redundancy erase mode is enabled, the controller checks whether a column address of a memory bank to be accessed is repaired or not, and generates an internal column address and a column select signal, and the memory area further comprises main storage units coupled to the respective main memory areas and redundancy storage units coupled to the respective redundancy memory areas, and the controller comprises: an address generator configured to generate the internal column address according to whether the column address is repaired or not; and a storage unit selector configured to generate the column select signal in response to the internal column address and a storage unit select signal.