Semiconductor structures with pair(s) of vertical field effect transistors, each pair having a shared source/drain region and methods of forming the structures

摘要

Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).

主权项

1. A method of forming a semiconductor structure, said method comprising:
forming a pair of vertical field effect transistors on an insulator layer, said forming of said pair comprising:
forming an essentially U-shaped monocrystalline semiconductor body comprising:
a horizontal section immediately adjacent to said insulator layer;a first vertical section extending vertically from a first end of said horizontal section and having a first outer vertical surface and a first inner vertical surface opposite said first outer vertical surface; and,a second vertical section parallel to said first vertical section and extending vertically from a second end of said horizontal section opposite said first end, said second vertical section having a second inner vertical surface and a second outer vertical surface opposite said second inner vertical surface and said horizontal section having edges at said first end and said second end that are vertically aligned with said first outer vertical section of said first vertical section and said second outer vertical surface of said second vertical section;depositing dielectric material over said monocrystalline semiconductor body and said insulator layer;etching back said dielectric material to expose said first vertical section and said second vertical section, said etching back being performed such that said horizontal section between said first vertical section and said second vertical section remains covered by a first portion of said dielectric material and such that a second portion of said dielectric material that is thicker than said first portion remains above said insulator layer positioned laterally adjacent to said edges; and,after said etching back, forming, above said dielectric material, a first gate adjacent to said first vertical section and a second gate adjacent to said second vertical section; and, forming a contact positioned laterally between and electrically isolated from said first gate and said second gate, said contact extending vertically to a center portion of said horizontal section.