CMOS nanowire structure

摘要

Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

主权项

1. A semiconductor structure, comprising:
a first semiconductor device comprising:
a first plurality of vertically stacked nanowires disposed above a substrate, the bottom most nanowire of the first plurality of vertically stacked nanowires having a mid-point a first distance above the substrate, and each of the nanowires of the first plurality of vertically stacked nanowires comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region;a first gate electrode stack completely surrounding the discrete channel region of each of the nanowires of the first plurality of vertically stacked nanowires; anda first pair of contacts completely surrounding the discrete source and drain regions of each of the nanowires of the first plurality of vertically stacked nanowires; and a second semiconductor device comprising:
a second plurality of vertically stacked nanowires disposed above the substrate, the bottom most nanowire of the second plurality of vertically stacked nanowires having a mid-point a second distance above the substrate, and each of the nanowires of the second plurality of vertically stacked nanowires comprising a discrete channel region and discrete source and drain regions on either side of the discrete channel region, the first distance different from the second distance;a second gate electrode stack completely surrounding the discrete channel region of each of the nanowires of the second plurality of vertically stacked nanowires; anda second pair of contacts completely surrounding the discrete source and drain regions of each of the nanowires of the second plurality of vertically stacked nanowires.