发明名称 Digital wideband closed loop phase modulator with modulation gain calibration
摘要 One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.
申请公布号 US9225562(B2) 申请公布日期 2015.12.29
申请号 US201213405583 申请日期 2012.02.27
申请人 Intel Deutschland GmbH 发明人 Mayer Thomas;Bauernfeind Thomas;Wicpalek Christian
分类号 H04L27/12;H04L25/03;H04L27/20 主分类号 H04L27/12
代理机构 Eschweiler & Associates, LLC 代理人 Eschweiler & Associates, LLC
主权项 1. A modulation system comprising: a phase locked loop configured to receive an input signal generate an error signal and an output signal; a digital to time converter configured to phase shift the output signal according to an adaptive signal; an adaptive control configured to receive the error signal from the phase locked loop and to provide the adaptive signal to the digital to time converter; and wherein the adaptive control signal is configured to generate the adaptive signal according to the error signal, wherein the adaptive signal generated by the adaptive control is a control signal and mitigates gain errors for the digital to time converter component of the phase locked loop.
地址 Neubiberg DE
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