发明名称 情報処理装置及び情報処理装置制御方法
摘要 A reception circuit receives data using a plurality of lanes. When a failure occurs in one of the lanes, an all lanes control unit (505) degenerates a predetermined number of lanes including the lane in which the failure has occurred. Then, a continuously-operated lane control unit (504) causes the reception circuit to receive the data using remaining lanes except for the predetermined number of degenerated lanes among the lanes. A degenerated lane control unit (503) performs retraining to establish links in the predetermined number of lanes. When the links are established by the retraining with the degenerated lane control unit (503), an all lanes control unit (505) causes the reception circuit to receive the data using the predetermined number of lanes and the remaining lanes.
申请公布号 JP5835464(B2) 申请公布日期 2015.12.24
申请号 JP20140507205 申请日期 2012.03.29
申请人 富士通株式会社 发明人 前田 晃一;早坂 和美
分类号 H04L29/00;G06F13/36 主分类号 H04L29/00
代理机构 代理人
主权项
地址