METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION

摘要

Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

主权项

1. A method for partial binary translation, the method comprising:
determining if an instruction has an invalid opcode; determining whether or not the instruction needs to be translated; generating a partial translation of an executable region containing the invalid opcode, the partial translation including at least an encapsulation of a binary translation of the invalid opcode and a state recovery mechanism for a first machine state prior to the execution of the invalid opcode; storing the partial translation in a cache memory; and storing an indicator of the partial translation associated with the invalid opcode.