ARRAY SENSOR APPARATUS AND FORMING METHOD THEREOF

摘要

An array sensor apparatus and forming method thereof, wherein the array sensor comprises: a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are formed on the same substrate surface, the sensor circuit comprises a pixel cell array including pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor. In the array sensor apparatus of the present disclosure, the driving circuit and the sensor circuit are formed on the same substrate surface, thus occupying less area. Reliability may be improved. Besides, the forming processes can be implemented simultaneously without additional processing steps.

主权项

1. An array sensor, comprising:
a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are configured onto a same substrate surface, the sensor circuit comprises a pixel cell array comprising pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor; wherein the first transistor comprises: a first conductive layer located on the substrate surface; a first insulating layer overlaying the first conductive layer; a first semiconductor layer located on a surface of the first insulating layer, wherein position of the first semiconductor corresponds to position of the first conductive layer; a second conductive layer overlaying the first semiconductor layer, wherein the second conductive layer has a first opening which partially exposes a surface of the first semiconductor layer; a second insulating layer overlaying the second conductive layer and filling up the first opening; and a first barrier layer located on a surface of the second insulating layer, wherein position of the first barrier layer corresponds to position of the first opening; and wherein the second transistor comprises: a third conductive layer located on the substrate surface; a third insulating layer overlaying the third conductive layer; a second semiconductor layer located on a surface of the third insulating layer, wherein position of the second semiconductor layer corresponds to position of the third conductive layer; a forth conductive layer overlaying the second semiconductor layer, wherein the forth conductive layer has a second opening which partially exposes a surface of the second semiconductor layer; a forth insulating layer overlaying the forth conductive layer and filling up the second opening; and a second barrier layer located on a surface of the forth insulating layer, wherein position of the second barrier layer corresponds to position of the second opening.