Three Dimensional Vertical NAND Device With Floating Gates

摘要

A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

主权项

1. A monolithic three dimensional NAND string, comprising:
a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate, wherein:
the first material layers comprise a plurality of control gate electrodes and the second material layers comprise an insulating material; andthe plurality of control gate electrodes extend in a first direction substantially parallel to the major surface of the substrate and comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located above the first device level; a semiconductor channel comprising at least one portion extending through the stack in a second direction substantially perpendicular to the major surface of the substrate; a blocking dielectric located in contact with the plurality of control gate electrodes; a plurality of vertically spaced apart floating gates, wherein the plurality of vertically spaced apart floating gates comprise at least a first spaced apart floating gate located in the first device level and a second spaced apart floating gate located in the second device level; and a tunnel dielectric located between each one of the plurality of the vertically spaced apart floating gates and the semiconductor channel;
wherein each of the plurality of vertically spaced apart floating gates or each of the second material layers comprises a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.