METHOD FOR ADJUSTING A TIMING DERATE FOR STATIC TIMING ANALYSIS

摘要

A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

主权项

1. A computer-implemented static timing analysis method for determining an expected timing of a signal path of an integrated circuit design, the method comprising:
determining a timing derate for a target cell on the signal path, the timing derate representing variation in a propagation delay through the target cell for a default design condition surrounding the target cell; determining an expected design condition surrounding the target cell in the integrated circuit design; determining a derate adjustment based on the expected design condition of the target cell; adjusting the timing derate using the derate adjustment to generate an adjusted timing derate; and determining the expected timing of the signal path based on the adjusted timing derate for the target cell.