发明名称 |
LAYOUT DESIGN METHOD AND SYSTEM |
摘要 |
A layout design method is disclosed. The layout design method includes: (a) providing an original layout file; (b) performing a redundant via (RV) filling on the original layout file so as to generate a second layout file; (c) merging the second layout file with the original layout file to generate a third layout file; (d) performing a design rule check (DRC) verification on the third layout file by directly invoking a DRC code in a Process Design Kit (PDK); (e) generating, based on a result of the DRC verification, a fourth layout file including DRC errors; (f) performing a layout operation to remove DRC errors from the second layout file using the fourth layout file, so as to generate a fifth layout file; and (g) merging the fifth layout file with the original layout file to generate a sixth layout file. |
申请公布号 |
US2015370957(A1) |
申请公布日期 |
2015.12.24 |
申请号 |
US201514735952 |
申请日期 |
2015.06.10 |
申请人 |
Semiconductor Manufacturing International (Shanghai) Corporation |
发明人 |
FAN Qiang;LI Xue |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A computer-implemented layout design method, the method to be performed by a system comprising at least one processor and at least one memory, the method comprising:
(a) providing an original layout file; (b) performing a redundant via (RV) filling on the original layout file so as to generate a second layout file; (c) merging the second layout file with the original layout file to generate a third layout file; (d) performing a design rule check (DRC) verification on the third layout file by directly invoking a DRC code in a Process Design Kit (PDK); (e) generating, based on a result of the DRC verification, a fourth layout file including DRC errors; (f) performing a layout operation to remove DRC errors from the second layout file using the fourth layout file, so as to generate a fifth layout file; and (g) merging the fifth layout file with the original layout file to generate a sixth layout file. |
地址 |
Shanghai CN |