Pattern Layout to Prevent Split Gate Flash Memory Cell Failure

摘要

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

主权项

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:
a semiconductor substrate including a first source/drain region and a second source/drain region, wherein a channel region is arranged between the first and second source/drain regions; a select gate and a memory gate spaced between the first and second source/drain regions over the channel region, wherein the select gate extends over the channel region and terminates at a line end having a top surface being asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate; and a charge trapping dielectric structure arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate.