SYSTEM-IN-PACKAGES HAVING VERTICALLY-INTERCONNECTED LEADED COMPONENTS AND METHODS FOR THE FABRICATION THEREOF

摘要

System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.

主权项

1. A method for producing a System-in-Package, the method comprising:
providing a core package comprising a molded body, a semiconductor die embedded in the molded body, and at least one Redistribution Layer (RDL) formed over the molded body and containing an interconnect line; removing material from the core package to form a through-hole extending through the molded body and through the at least one RDL at a location intersecting the interconnect line such that the interconnect line terminates and exposed at a sidewall surface of the through-hole; positioning a leaded component adjacent the core package such that an elongated lead of the leaded component extends into the through-hole; and applying an electrically-conductive material into the through-hole to electrically couple the elongated lead of the leaded component to the interconnect line contained within the at least one RDL.