发明名称 3次元構造のメモリ素子を製造する装置
摘要 Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.
申请公布号 JP5836431(B2) 申请公布日期 2015.12.24
申请号 JP20140117902 申请日期 2014.06.06
申请人 ユ−ジーン テクノロジー カンパニー.リミテッド 发明人 チョ,ソン キル;キム,ハイ ウォン;ウ,サン ホ;シン,スン ウ;チャン,キル ソン;オ,ワン スク
分类号 H01L21/8247;C23C16/458;H01L21/31;H01L21/336;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
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