VIA PLACEMENT WITHIN AN INTEGRATED CIRCUIT

摘要

An integrated circuit layout 2 is formed by performing a routing step forming a routing layout of routing conductors 26 and routing connection vias 28 prior to performing a power grid connection step which forms power connection vias 24 between power grid conductors 22 and standard-power cell conductors 20 within the standard cells 6. This enables a minimum via spacing requirement to be met whilst permitting an increased flexibility in the positioning of the routing connection vias.

主权项

1. A method of forming a layout of an integrated circuit having:
a plurality of standard cells connected to draw power from standard-cell power conductors in a standard-cell conductor layer; and a plurality of power grid conductors disposed overlapping at least portions of said plurality standard-cell power conductors in a further layer separate from said standard-cell conductor layer, said method comprising the steps of: a routing step forming a routing layout of routing conductors and routing connection vias to connect different portions of said plurality of standard cells; and subsequent to said routing step, a power grid connection step forming a power connection via layout of power connection vias to connect said plurality of power grid conductors to said plurality of standard-cell power conductors, wherein said power grid connection step is responsive to positions of said routing connection vias determined in said routing step to position said power grid connection vias at positions meeting a minimum via spacing requirement from said routing connection vias.