发明名称 |
A MARCHING MEMORY, A BIDIRECTIONAL MARCHING MEMORY, A COMPLEX MARCHING MEMORY AND A COMPUTER SYSTEM, WITHOUT THE MEMORY BOTTLENECK |
摘要 |
A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor. |
申请公布号 |
EP2815403(A4) |
申请公布日期 |
2015.12.23 |
申请号 |
EP20130748879 |
申请日期 |
2013.02.13 |
申请人 |
NAKAMURA, TADAO;FLYNN, MICHAEL J. |
发明人 |
NAKAMURA, TADAO;FLYNN, MICHAEL J. |
分类号 |
G11C19/28;G11C19/18 |
主分类号 |
G11C19/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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